FMC Loopback Adapter

The DFMC-TESTADP is an FPGA Mezzanine Card (FMC) for testing FMC Carriers. It is a tool for FMC carrier developers for testing the full characteristics of their FMC carrier interface. The TESTADP features loopbacks on all FMC differential pairs on the HPC connectors. Furthermore it provides an on board, user programmable low jitter clock generator supporting reference clocks which are required for PCIe, SATA, SRIO, Fiber Channel or Gbit Ethernet protocols. It checks also the supply voltage of the FMC carrier connections.
Applications:
• FMC carrier board testing during development
• FMC carrier board electrical validation

Applications
  • FMC carrier board testing during development
  • FMC carrier board electrical validation
Main Features
  • FMC form factor
  • High pin count interface (HPC)
  • FMC clock generator
  • FMC HA, HB and LA differential pairs loopbacks
  • FMC DP differential pairs loopbacks
  • 8-channel ADC for checking supply voltages
  • All signals can be checked (including JTAG, Power Good...)
DFMC-TESTADP
Datasheet

Location: /afs/desy.de/group/msk/www/html/TechLab/DFMC-TESTADP

Licensing

DESY offers the DFMC-TESTADP for licensing to industry. DESY can modify this product to meet special customer requirements.