FMC Direct-Sampling A-D Converter

The DFMC-DS500/800 is a FPGA mezzanine card (FMC) carrying a mid to high speed digitizer. It is fully ANSI/VITA 57.1 compliant. The FMC has a high pin count connector with a stacking height of 8.5mm and therefore it is fully air cooled.
The FMC offers a dual channel 12-bit ADC with 500/800 MSP/s. There are also variants with up to 1.6 GSP/s per channel and 10-bits resolution available. The DS500/800 supports AC and DC single ended input signals with a level up to 1Vp-p. The input bandwidth is >2.5 GHz (TBD). The digital interfaces to the FPGA are 2x 13-bits parallel LVDS.
Versatile clocking options are offered by the DS500/800. One can feed in the ADC clock directly via a front panel connector. There is a high precision TCXO combined with a multi loop PLL on the board available. The PLL consists of an ultra-low phase noise VCSO and a custom build loop filter. A clock monitoring output is also located at the front panel.
For triggering there are 4 LVDS and 2 single ended inputs on the front panel. These trigger signals can be configured as general purpose inputs and outputs.

Main Features
  • Single Size FPGA mezzanine card (FMC)
  • ANSI/VITA 57.1 standard conform High-Pin-Count module
  • 12-bits, 500/800 MSP/s dual ch., 1/1.6 GSP/s dingle ch. ADC
  • ADC analogue input bandwidth: >2.5 GHz
  • Amplifier LS bandwidth: 4.8 GHz, ac / dc coupled inputs
  • Ext. clock input connector, high stability TCXO, ultra-low phase noise PLL with VCSO on-board
  • 8.5 mm stacking height, air cooled
  • front panel: 5 RF SSMC + 1 HDMI Type D (micro) connectors
  • Up to 6 Trigger / GPIO signals (4 LVDS differential + 2 single ended 3.3V)
  • User EEPROM for calibration data
  • RoHS compliant
DFMC-DS800
Licensing

DESY offers the DFMC-DS800 for licensing to industry. DESY can modify this product to meet special customer requirements.

Datasheet
application/pdf Datasheet (1.0 MB)
Datasheet